Modern microprocessors often have embedded cache memory and cache memory control to allow for faster read/write access to main memory. Typically, cache memory is SRAM-based (Static Random Access Memory), having access times on the order of 20 nanoseconds (ns), and the main memory is DRAM-based (Dynamic Random Access Memory), having access times on the order of 80-150 ns. While SRAM is generally faster, it is generally more expensive than DRAM. However, the cost/performance tradeoff can be minimized by using a relatively small cache (e.g., 32 Kbytes) to provide quick access to blocks of a relatively large main memory. Various algorithms are known and employed to manage cache operation, but the present invention is not limited by the choice of algorithm.
U.S. Pat. No. 4,945,512, issued Jul. 31, 1990, discloses a high speed associative cache memory wherein each of four data array boards comprise a quarter word data array, a full tag array and a memory address register. Each (quarter word) data array board also includes a match comparator for comparing the tag portion of the memory address to the output of the tag array, and generates four tag compare signals which are applied to monitoring and error detection circuits.
U.S. Pat. No. 4,945,472, issued Jul. 31, 1990, discloses a data processor with I/O area detection, and is illustrative of a data processing system having a data processor, memory, and I/O interface, all of which are interconnected via an address bus, a data bus and a control bus.
U.S. Pat. No. 4,937,781, issued Jun. 26, 1990, discloses a dual port ram with arbitration status register, and is illustrative of a multi-port RAM having an array of memory locations for storing data, with each of the memory locations having an address associated therewith.
U.S. Pat. No. 4,937,738, issued Jun. 26, 1990, discloses a data processing system which selectively bypasses a cache memory in fetching information based upon bit information of an instruction, wherein a particular region of memory is assigned for data that is to be used repeatedly. When data is to be read out from other regions, operation of the memory is executed immediately without waiting for the reference of cache memory.
These patents are cited as representative of the general state of the art dealing with cache memory management.
FIG. 1 shows a typical cache architecture 100. Main memory (not shown) is accessed by a microprocessor (not shown) over an address bus 102 and a data bus 104. In this example, the address bus 102 is 32 bits wide (A31..A0), for accessing up to a gigabyte of main memory, and the data bus is 32 bits wide (D31..D0).
Cache memory 106 is divided into portions (parts)--a "data" part 108 and a "tag" part 110. In this example, the size of the data part 108 is 32K.times.32 (for storing 32K 32-bit words). In practice, the 32K.times.32 data part 108 may be formed as a 128K.times.8 SRAM array.
When, for instance, a data write cycle is initiated, a low order portion (A16..A2) of the (main memory) address is provided to the data part 108. This may involve stripping the low order portion of the address off a full 32-bit data bus, or by providing separate low order (AdrLo) and high order (AdrHi) portions of the address bus. The low order portion (A16..A2) of the address corresponds on a one-to-one basis with the 32K physical locations (P14..P0) in the data part 108, and is used to select one of those locations, or "cells", for example location "AF73-data" (hex), for storing a data word. (The first two bits A0,A1 of the address may be used for byte gathering, i.e. for assembling four 8-bit bytes into a 32 bit word.) The 32-bit data word (D0..D31) corresponding to the full address is provided over the data bus 104 to the selected location ("AF73-data") in the data part 108.
The tag part 110 has 32K physical locations (T14..T0). The higher order portion (A31..A17) of the address (A0..A30) is provided to the tag part 110 in a location corresponding on a one-to-one basis to the selected location (AF73-data) of the stored data in the data part 108. In this example, the higher order portion of the address (A31..A17) would be stored in location "AF73-tag" in the tag part 110.
Evidently, the tag part 110 can be smaller than the data part 108. In this example, the tag part is 32K.times.14.
Hence, the total address (A31..A0) is ultimately represented by corresponding physical locations in the data and tag parts (AF73-data=AF73-tag=A16..A2), and the higher order portion (A31..A17) stored in the tag part.
Data stored in cache memory can be either "data" or "instructions". In many cases, cache memory is segmented into a "data" cache (DCache) having a data part and a tag part, and an "instruction" cache (ICache) having a data part (containing "instructions") and a tag part. Functionally, the data cache and instruction cache operate identically, although they may be sized differently. For tee most part hereinafter, discussion directed to data cache is applicable to instruction cache.
Evidently, verifying proper operation of an embedded cache is more difficult than testing an external cache. Nevertheless, testing the data (or instruction) part is relatively straightforward. The contents of selected locations of the data part 112 are read, or tested (by the microprocessor, not shown) against what was written thereto.
Testing the tag part is somewhat more involved. Typically, to verify operation of the tag part, a read operation is initiated, such as by providing an address over the address bus 102. The stored tag (T14..T0) is compared in a comparator 112 with the higher order portion of the address (A31..A17), taken directly from the bus. If they compare, a "hit" signal issues from the comparator. If they mis-match, a "miss" signal issues.
It is virtually a necessity to exercise and test the integrity of cache memory. In the past, this has involved testing the memory (RAM) off-line. In the context of an embedded cache memory, such as disclosed herein, existing testing techniques are not feasible.